Make is a fancy scripting mechanism, and a very powerful one at that.

A "Make File" consists of a series of rules.  Each of these rules are designed to perform some type of task on demand.  Some of the rules are very simplistic, such as:

myfile.o: myfile.c

{tab}gcc -o myfile.o myfile.c

Now, if there is any rule in the makefile that requires myfile.o (this rule requires myfile.c), it will execute this rule, which simply states, myfile.o needs to be rebuilt it myfile.c has changed, and if it needs to be rebuilt, use the following command (the gcc command on the next line) to build it.  So, I can now create my executable by typing:

myfile: myfile.o

{tab}gcc -o myfile myfile.o

OK, so much for the super simple stuff, time for the basically simple stuff.

My compiler is not likely to change from one c file to another... so I can create a macro for it, it is generally called CC by convention.  I will also want to use the same C compiler flags on all my objects so I will call that CFLAGS by convention.  And, I don't really want to specify every object and convention file individually, that could get tedious.  So, I can change my first line to read like this:

.c.o:

And since I don't know the name of the file, make allows me to use a place holder for the first entry like so: $< and the second value like so: $@.  Now I can rebuild my rule like thus:

CC=gcc

CLIBS="-c"

myfile:myfile.o

{tab}gcc -o myfile myfile.o

.c.o:

{tab}$(CC) $(CFLAGS) -o $< $@

Looks greek, but its really pretty straightforward.  Oh, in case you are wondering how does it determine if the .o file needs to be rebuilt?  simple, if the time-stamp on the .c file is later than the .o file, rebuild the .o file, as the .c file is newer.  Again, not too tough.

But lets say you want to do some administrative tasks also.  Some of the common ones are "TEST", "CLEAN", "INSTALL", etc.  I can simple create a label and indent my commands with a tab character.  So, to delete all the .o files so that everything is recompiled:

clean:

{tab}rm -rf *.o

Now, if you execute "make clean" on the command line, make will look for a label called clean, and execute whatever is there.  If you do not specify a label (i.e. you just type make), it will execute the first label it sees.  So in allot of make files you will see a label of "ALL" at the top to make the default to make the entire project.

I hope my 101 introduction to Make makes sense.

Kevin

On Mon, Jul 28, 2014 at 2:11 PM, Michael Havens <bmike1@gmail.com> wrote:

what does that command do? I thought that it installed what you compiled with make. but at as I am working through linux from scratch I get to perl and it says:

Only a few of the utilities and libraries, need to be installed at this time:
cp -v perl cpan/podlators/pod2man /tools/bin
mkdir -pv /tools/lib/perl5/5.18.2
cp -Rv lib/* /tools/lib/perl5/5.18.2

so is it installing the files with cp?  is 'make install' just another way to say 'cp'?

:-)~MIKE~(-:

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